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RT8068A 1 ds8068a-03 may 2011 www.richtek.com applications z portable instruments z battery powered equipment z notebook computers z distrib uted power systems z ip phones z digital cameras pin configurations (top view) wdfn-10l 3x3 3a, 1mhz, synchronous step-down converter general description the RT8068A is a high efficiency synchronous, step-down dc/dc converter. it's input voltage range from 2.7v to 5.5v that provides an adjustable regulated output voltage from 0.6v to v in while delivering up to 3a of output current. the internal synchronous low on resistance power switches increase efficiency and eliminate the need for an external schottky diode. the switching frequency is fixed internally at 1mhz. the 100% duty cycle provides low dropout operation, hence extending battery life in portable systems. current mode operation with internal compensation allows the transient response to be optimized over a wide range of loads and output capacitors. the RT8068A is available in wdfn-10l 3x3 and sop-8 (exposed pad) packages. ordering information note : richtek products are : rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. suitable for use in snpb or pb-free soldering processes. features z z z z z high efficiency : up to 95% z z z z z low r ds(on) internal switches : 69m /49m at v in = 5v z z z z z fixed frequency : 1mhz z z z z z no schottky diode required z z z z z internal compensation z z z z z 0.6v reference allows low output voltage z z z z z low dropout operation : 100% duty cycle z z z z z ocp, uvp, ovp, otp z z z z z rohs compliant and halogen free sop-8 (exposed pad) 9 8 7 1 2 3 4 5 10 6 gnd 11 lx pgood lx en lx pvin nc pvin svin fb lx lx pgood en pvin pvin fb svin gnd 2 3 4 5 6 7 8 9 marking information 13 : product code ymdnn : date code RT8068Azqw RT8068Azsp : product code ymdnn : date code RT8068Azsp RT8068A zspymdnn 13 ym dnn package type qw : wdfn-10l 3x3 (w-type) sp : sop-8 (exposed pad-option 2) RT8068A lead plating system z : eco (ecological element with halogen free and pb free)
RT8068A 2 ds8068a-03 may 2011 www.richtek.com pin no. wdfn-10l sop-8 (exposed pad) pin name pin function 1, 2, 3 1, 2 lx switch node. connect this pin to the inductor. 4 3 pgood power good indicator. this pin is an open drain logic output that is pulled to ground when the output voltage is less than 90% of the target output voltage. hysteresis = 5%. 5 4 en enable control. pull high to turn on. do not float. 6 5 fb feedback pin. this pin receives the feedback voltage from a resistive voltage divider connected across the output. 7 -- nc no internal connection. 8 6 svin signal input pin. decouple this pin to gnd with at least 1 f ceramic cap. 9,10 7,8 pvin power input pin. decouple this pin to gnd with at least 4.7 f cer amic cap. 11 (exposed pad) 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. functional pin description typical application circuit table 1. recommended component selection v out (v) r fb1 (k ) r fb2 (k ) c ff (pf) l ( h) c out ( f) 3.3 229.5 51 22 2 22 x 2 2.5 161.5 51 22 2 22 x 2 1.8 102 51 22 1.5 22 x 2 1.5 76.5 51 22 1.5 22 x 2 1.2 51 51 22 1.5 22 x 2 1.0 34 51 22 1.5 22 x 2 l gnd lx RT8068A v out pvin fb v in r fb1 r fb2 c in c ff pgood en r1 c out svin c1 pgood chip enable 100k 10f 1f
RT8068A 3 ds8068a-03 may 2011 www.richtek.com function block diagram driver nisen control logic zero current 0.72v 0.54v 0.4v oc limit isen slope com osc output clamp ea 0.6v int-ss por otp en fb pvin svin en lx pgood pgood v ref ov uv pgood
RT8068A 4 ds8068a-03 may 2011 www.richtek.com parameter symbol test conditions min typ max unit feedback reference voltage v ref 0.594 0.6 0.606 v feedback leakage current i fb -- 0.1 0.4 a active , v fb = 0.7v, not switching -- 110 140 dc bias current shutdown -- -- 1 a output voltage line regulation v in = 2.7v to 5.5v i ou t = 0a -- 0.3 -- %/v output voltage load regulation i ou t = 0a to 3a ? 1 -- 1 % switch leakage current -- -- 1 a switching frequency 0.8 1 1.2 mhz switch on resistance, high r ds(on)_p v in = 5v -- 69 -- m switch on resistance, low r ds(on)_n v in = 5v -- 49 -- m p-mosfet current limit i lim 4 -- -- a v in rising 2.2 2.4 2.6 under voltage lockout threshold v uvlo v in falling 2 2.2 2.4 v (v in = 3.3v, t a = 25 c, unless otherwise specified) electrical characteristics recommended operating conditions (note 4) z supply input voltage, pvin, svin --------------------------------------------------------------------------------- 2.7v to 5.5v z junction temperature range ---------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ---------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply input v oltage, pvin, svin --------------------------------------------------------------------------------- ? 0.3v to 6.5v z lx pin dc ------------------------------------------------------------------------------------------------------------------------- ( v in + 0.3v) to 6.8v < 20ns ------------------------------------------------------------------------------------------------------------------- ? 2.5v to 9v z other i/o pin voltage ------------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z power dissipation, p d @ t a = 25 c wdf n-10l 3x3 --------------------------------------------------------------------------------------------------------- 1.429w sop-8 (exposed pad) ----------------------------------------------------------------------------------------------- 1.333w z package thermal resistance (note 2) wdfn-10l 3x3, ja --------------------------------------------------------------------------------------------------- 70 c/w wdfn-10l 3x3, jc --------------------------------------------------------------------------------------------------- 8.2 c/w sop-8 (exposed pad), ja ------------------------------------------------------------------------------------------ 75 c/w sop-8 (exposed pad), jc ----------------------------------------------------------------------------------------- 15 c/w z lead temperature (soldering, 10 se c.) --------------------------------------------------------------------------- 260 c z junction temperature ------------------------------------------------------------------------------------------------- 150 c z storage temperature range ---------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------------------------ 2kv mm (ma chine mode) -------------------------------------------------------------------------------------------------- 200v to be continued
RT8068A 5 ds8068a-03 may 2011 www.richtek.com parameter symbol test conditions min typ max unit logic-high v ih 1.6 -- -- en input threshold voltage logic-low v il -- -- 0.4 v en pull low resistance -- 500 -- k over temperature protection t sd -- 150 -- c over temperature protection hysteresis -- 20 -- c soft-start time t ss 500 -- -- s v out discharge resistance -- 100 -- v out over voltage protection (latch-off, delay time = 10 s) 115 120 130 % v out under voltage lock out (latch-off) 57 66 75 % power good measured fb, with respect to v ref 85 90 -- % power good hysteresis -- 5 -- % note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the packages. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT8068A 6 ds8068a-03 may 2011 www.richtek.com typical operating characteristics output voltage vs. output current 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 0 0.5 1 1.5 2 2.5 3 output current (a) output voltage (v) v in = 5v v out = 1.8v v in = 3.3v current limit vs. input voltage 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 2.533.544.555.5 input voltage (v) current limit (a) v out = 1.05v current limit vs. temperature 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 -50 -25 0 25 50 75 100 125 temperature (c) current limit (a) v in = 5v v out = 1.05v v in = 3.3v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 00.511.522.53 load current (a) efficiency (%) v out = 1.05v v in = 3.3v v in = 5v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 load current (a) efficiency (%) v out = 3.3v v in = 4.2v v in = 5v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 00.511.522.53 load current (a) efficiency (%) v out = 1.8v v in = 3.3v v in = 5v
RT8068A 7 ds8068a-03 may 2011 www.richtek.com r ds(on) vs. temperature 35 40 45 50 55 60 65 70 75 80 85 90 -50 -25 0 25 50 75 100 125 temperature (c) r ds(on) (m ? ) p-mosfet v in = 5v n-mosfet over voltage protection time (10 s/div) v in = 5v, v out = 1.8v, i out = 1a v out (1v/div) v lx (2v/div) load transient response time (50 s/div) v in = 5v, v out = 1.8v, i out = 0.5a to 3a i out (2a/div) v out (50mv/div) load transient response time (50 s/div) v in = 5v, v out = 1.8v, i out = 1.5a to 3a i out (2a/div) v out (50mv/div) switching time (500ns/div) v in = 5v, v out = 1.8v, i out = 3a i lx (2a/div) v lx (5v/div) v out (5mv/div) switching time (500ns/div) v in = 5v, v out = 1.8v, i out = 1.5a i lx (1a/div) v lx (5v/div) v out (5mv/div)
RT8068A 8 ds8068a-03 may 2011 www.richtek.com over current protection time (2.5 s/div) v in = 5v, v out = 1.8v v out (1v/div) v lx (2v/div) i lx (5a/div) power on from v in time (2.5ms/div) v out = 1.8v, i out = 3a i lx (2a/div) v out (1v/div) v in (2v/div) power off from v in time (2.5ms/div) v out = 1.8v, i out = 3a i lx (2a/div) v out (1v/div) v in (2v/div) power on from en time (200 s/div) v out (1v/div) v en (5v/div) i lx (2a/div) v in = 5v, v out = 1.8v, i out = 3a power off from en time (40 s/div) v out (1v/div) v en (5v/div) i lx (2a/div) v in = 5v, v out = 1.8v, i out = 3a under voltage protection time (5 s/div) v in = 5v, v out = 1.8v v out (1v/div) v lx (2v/div)
RT8068A 9 ds8068a-03 may 2011 www.richtek.com application information the RT8068A is a single-phase buck converter. it provides single feedback loop, current mode control with fast transient response. an internal 0.6v reference allows the output voltage to be precisely regulated for low output voltage applications. a fixed switching frequency (1mhz) oscillator and internal compensation are integrated to minimize external component count. protection features include over current protection, under voltage protection, over voltage protection and over temperature protection. output voltage setting connect a resistive voltage divider at the fb between v out and gnd to adjust the output voltage. the output voltage is set according to the following equation : chip enable and disable the en pin allows for power sequencing between the controller bias voltage and another voltage rail. the RT8068A remains in shutdown if the en pin is lower than 400mv. when the en pin rises above the v en trip point, the RT8068A begins a new initialization and soft-start cycle. internal soft-start the RT8068A provides an internal soft-start function to prevent large inrush current and output voltage overshoot when the converter starts up. the soft-start (ss) automatically begins once the chip is enabled. during soft- start, the internal soft-start capacitor becomes charged and generates a linear ramping up voltage across the capacitor. this voltage clamps the voltage at the fb pin, causing pwm pulse width to increase slowly and in turn reduce the output surge current. the internal 0.6v reference takes over the loop control once the internal ramping-up voltage becomes higher than 0.6v. fb1 out ref fb2 r v = v 1 + r ?? ?? ?? where v ref is 0.6v (typ.). figure 1. setting v out with a voltage divider uvlo protection the RT8068A has input under voltage lockout protection (uvlo). if the input voltage exceeds the uvlo rising threshold voltage (2.4v typ.), the converter resets and prepares the pwm for operation. if the input voltage falls below the uvlo falling threshold voltage during normal operation, the device will stop switching. the uvlo rising and falling threshold voltage has a hysteresis to prevent noise-caused reset. inductor selection the switching frequency (on-time) and operating point (% ripple or lir) determine the inductor value as shown below: ( ) out in out sw load(max) in vv v l = f lir i v ? where lir is the ratio of the peak-to-peak ripple current to the average inductor current. find a low loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ) : peak load(max) load(max) lir i = i + i 2 ?? ?? ?? the calculation above serves as a general reference. to further improve transient response, the output inductor can be further reduced. this relation should be considered along with the selection of the output capacitor. input capacitor selection high quality ceramic input decoupling capacitor, such as x5r or x7r, with values greater than 20 f are recommended for the input capacitor. the x5r and x7r ceramic capacitors are usually selected for power regulator capacitors because the dielectric material has less capacitance variation and more temperature stability. voltage rating and current rating are the key parameters when selecting an input capacitor. generally, selecting an input capacitor with voltage rating 1.5 times greater than the maximum input voltage is a conservatively safe design. fb gnd v out r fb1 r fb2
RT8068A 10 ds8068a-03 may 2011 www.richtek.com out out in_rms load in in vv i = i 1 vv ?? ? ?? ?? the next step is selecting a proper capacitor for rms current rating. one good design is using more than one capacitor with low equivalent series resistance (esr) in parallel to form a capacitor bank. the input capacitance value determines the input ripple voltage of the regulator. the input voltage ripple can be approximately calculated using the following equation : out(max) in in sw i0.25 v = cf for example, if i out_max = 3a, c in = 20 f, f sw = 1mhz, the input voltage ripple will be 37.5mv. output capacitor selection the output capacitor and the inductor form a low pass filter in the buck topology. in steady state condition, the ripple current flowing into/out of the capacitor results in ripple voltage. the output voltage ripple (v p-p ) can be calculated by the following equation : p_p load(max) out sw 1 v= liri esr + 8c f ?? ?? ?? for a given output voltage sag specification, the esr value can be determined. another parameter that has influence on the output voltage sag is the equivalent series inductance (esl). the rapid change in load current results in di/dt during transient. therefore, the esl contributes to part of the voltage sag. using a capacitor with low esl can obtain better transient performance. generally, using several capacitors connected in parallel can have better transient performance than using a single capacitor for the same total esr. unlike the electrolytic capacitor, the ceramic capacitor has relatively low esr and can reduce the voltage deviation when load transient occurs, the output capacitor supplies the load current before the controller can respond. therefore, the esr will dominate the output voltage sag during load transient. the output voltage undershoot (v sag ) can be calculated by the following equation : sag load v = i esr ? the input capacitor is used to supply the input rms current, which can be approximately calculated using the following equation : during load transient. however, the ceramic capacitor can only provide low capacitance value. therefore, use a mixed combination of electrolytic capacitor and ceramic capacitor to obtain better transient performance. power good output (pgood) pgood is an open-drain type output and requires a pull- up resistor. pgood is actively held low in soft-start, standby, and shutdown. it is released when the output voltage rises above 90% of nominal regulation point. the pgood signal goes low if the output is turned off or is 10% below its nominal regulation point. under voltage protection (uvp) the output voltage can be continuously monitored for under voltage. when under voltage protection is enabled, both ugate and lgate gate drivers will be forced low if the output is less than 66% of its set voltage threshold. the uvp will be ignored for at least 3ms (typ.) after start up or a rising edge on the en threshold. toggle en threshold or cycle v in to reset the uvp fault latch and restart the controller. over voltage protection (ovp) the RT8068A is latched once ovp is triggered and can only be released by toggling en threshold or cycling v in . there is a 10 s delay built into the over voltage protection circuit to prevent false transition. over current protection (ocp) the RT8068A provides over current protection by detecting high side mosfet peak inductor current. if the sensed peak inductor current is over the current limit threshold (4a typ.), the ocp will be triggered. when ocp is tripped, the RT8068A will keep the over current threshold level until the over current condition is removed. thermal shutdown (otp) the device implements an internal thermal shutdown function when the junction temperature exceeds 150 c. the thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal shutdown threshold. once the die temperature decreases below the hysteresis of 20 c, the device reinstates the power up sequence.
RT8068A 11 ds8068a-03 may 2011 www.richtek.com thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT8068A, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for sop-8 (exposed pad) packages, the thermal resistance, ja , is 75 c/w on a standard jedec 51-7 four-layer thermal test board. for wdfn-10l 3x3 packages, the thermal resistance, ja , is 70 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formulas : p d(max) = (125 c ? 25 c) / (75 c/w) = 1.333w for sop-8 (exposed pad) package p d(max) = (125 c ? 25 c) / (70 c/w) = 1.429w for wdfn-10l 3x3 package figure 2. derating curves for RT8068A packages 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb wdfn-10l 3x3 sop-8 (exposed pad) layout considerations layout is very important in high frequency switching converter design. the pcb can radiate excessive noise and contribute to converter instability with improper layout. certain points must be considered before starting a layout using the RT8068A. make the traces of the main current paths as short and wide as possible. put the input capacitor as close as possible to the device pins (v in and gnd). lx node encounters high frequency voltage swings so it should be kept in a small area. keep sensitive components away from the lx node to prevent stray capacitive noise pick-up. ensure all feedback network connections are short and direct. place the feedback network as close to the chip as possible. the gnd pin and exposed pad should be connected to a strong ground plane for heat sinking and noise protection. an example of pcb layout guide is shown in figure 3. for reference. the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the RT8068A package, the derating curves in figure 2 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 3. pcb layout guide r1 r2 c in2 c in1 r en r pgood v in v out c out gnd v out input capacitor must be placed as close to the ic as possible. lx should be connected to inductor by wide and short trace. keep sensitive components away from this trace. the output capacitor must be placed near the ic. the voltage divider must be connected as close to the device as possible. 9 8 7 1 2 3 4 5 10 6 gnd 11 lx pgood lx en lx pvin nc pvin svin fb
RT8068A 12 ds8068a-03 may 2011 www.richtek.com outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.500 1.750 0.059 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 10l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a
RT8068A 13 ds8068a-03 may 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138

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